FIELD OF THE INVENTION
The present invention relates to an RS flip-flop having an inverter connected to an input of the RS flip-flop, a NOR gate with an Enable-Set input, a NAND gate with an Enable-Reset input, and a first and a second transistor connected to the inverter.
FIG. 2 illustrates an exemplary embodiment of an RS flip-flop with Enable inputs. An input connection IN of the RS flip-flop is connected to an input of an inverter 1 whose output is connected to one input of an AND gate 2. The other input of the AND gate 2 is connected to an input which is an Enable-Set connection ENS. The output of the AND gate 2 is connected to the Set connection of a flip-flop 3. In addition, the input connection IN is connected to one input of a second AND gate 4 whose other input is connected to an input connection ENR for an Enable-Reset signal. The output of the second AND gate 4 is connected to the Reset input of the flip-flop 3.
In the circuit described above and also in the circuit described below, a signal at the connection ENS may be the inverse signal of a signal at the connection ENR (ENS=ENR).
FIG. 3 shows a specific circuit design with the flip-flop 3. NAND gates 5, 6 are used in place of the AND gates 2,4. The actual flip-flop 3 comprises two further NAND gates 7, 8. An output connection of each NAND gate 7, 8 is fed back to an input connection of the respective other NAND gate.
Irrespective of the specific design, the RS flip-flops shown in FIGS. 2 and 3 require a signal to pass through a total of three gates from the input connection IN to an output connection Q of the flip-flop 3. In the exemplary embodiment of FIG. 3, a signal has to pass through gates 1, 5, and 7. This results in a relatively long delay time (transit time), so that existing RS flip-flops are fairly slow and cannot provide or develop a pulse quickly.